This commit is contained in:
zhao
2023-01-18 00:20:52 -05:00
parent 02d5995ffd
commit 75dbf032ef
3 changed files with 6 additions and 3 deletions

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@ -4,6 +4,9 @@
- Finish refactoring files to use the application style, like in `yBar.scad` - Finish refactoring files to use the application style, like in `yBar.scad`
- Implement better build script using python - Implement better build script using python
- Finish side wall stuff
- Finish baseplate
- Start working on actual cases
### Ideas ### Ideas
@ -36,5 +39,5 @@ dx(yBarInnerYZ, mainRailSlot, sideConnectorSlot, includeFirst=true, includeLast=
// which would eval to: // which would eval to:
// x(yBarInnerYZ) + dx(yBarInnerYZ, mainRailSlot, sideConnectorSlot) + x(sideConnectorSlot); // x(yBarInnerYZ) + dx(yBarInnerYZ, mainRailSlot, sideConnectorSlot) + x(sideConnectorSlot);
``` ```
Hmm after looking into it a bit it seems that OpenScad's non-reassign rule is going to get in the way

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@ -50,7 +50,6 @@ module mainRail() {
} }
} }
module mainRailSharp() { module mainRailSharp() {
union() { union() {
_frontRailSegment(); _frontRailSegment();

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@ -9,7 +9,8 @@ include <./xyBarConnector.scad>
include <./yBar.scad> include <./yBar.scad>
include <./mainRail.scad> include <./mainRail.scad>
xBarDepth = maxUnitWidth - 2*railSlotSpacing; // It's actually the railSlotToInnerYEdge of the yBar, it'll be nice to be able to refer to it like yBar.railSlotToInnerYEdge
xBarDepth = maxUnitWidth - 2*railSlotToInnerYEdge;
xBarWidth = 32; xBarWidth = 32;
xBarHeight = 15; xBarHeight = 15;