From 75dbf032ef61235d1b09282117bfe3c7e70be76f Mon Sep 17 00:00:00 2001
From: zhao <jazhawang@gmail.com>
Date: Wed, 18 Jan 2023 00:20:52 -0500
Subject: [PATCH] fix xBar

---
 TODO.md            | 5 ++++-
 rack/mainRail.scad | 1 -
 rack/xBar.scad     | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/TODO.md b/TODO.md
index 49830cc..041a2b7 100644
--- a/TODO.md
+++ b/TODO.md
@@ -4,6 +4,9 @@
 
 - Finish refactoring files to use the application style, like in `yBar.scad` 
 - Implement better build script using python
+- Finish side wall stuff
+- Finish baseplate
+- Start working on actual cases
 
 ### Ideas
 
@@ -36,5 +39,5 @@ dx(yBarInnerYZ, mainRailSlot, sideConnectorSlot, includeFirst=true, includeLast=
 // which would eval to:
 // x(yBarInnerYZ) + dx(yBarInnerYZ, mainRailSlot, sideConnectorSlot) + x(sideConnectorSlot);
 ```
-
+Hmm after looking into it a bit it seems that OpenScad's non-reassign rule is going to get in the way 
 
diff --git a/rack/mainRail.scad b/rack/mainRail.scad
index e19fed2..caed1c2 100644
--- a/rack/mainRail.scad
+++ b/rack/mainRail.scad
@@ -50,7 +50,6 @@ module mainRail() {
     }
   }
 
-
   module mainRailSharp() {
     union() {
       _frontRailSegment();
diff --git a/rack/xBar.scad b/rack/xBar.scad
index 232504c..b4ecc8e 100644
--- a/rack/xBar.scad
+++ b/rack/xBar.scad
@@ -9,7 +9,8 @@ include <./xyBarConnector.scad>
 include <./yBar.scad>
 include <./mainRail.scad>
 
-xBarDepth = maxUnitWidth - 2*railSlotSpacing;
+// It's actually the railSlotToInnerYEdge of the yBar, it'll be nice to be able to refer to it like yBar.railSlotToInnerYEdge
+xBarDepth = maxUnitWidth - 2*railSlotToInnerYEdge;
 
 xBarWidth = 32;
 xBarHeight = 15;